The present disclosure relates to a semiconductor integrated circuit device including a standard cell with transistor having a fin structure.
A standard cell design has been known as a method of forming a semiconductor integrated circuit on a semiconductor substrate. The standard cell design refers to a method of designing a large-scale integrated circuit (LSI) chip by providing in advance, as standard cells, unit logic elements having particular logic functions (for example, an inverter, a latch, a flip-flop, and a full adder), laying out those standard cells on a semiconductor substrate, and connecting those standard cells together through a routing process.
Recently, it has been proposed to utilize transistors with a fin structure (hereinafter referred to as “fin transistors”) in the field of semiconductor devices. FIG. 14 schematically illustrates a fin transistor. Unlike a metal oxide semiconductor (MOS) transistor having a two-dimensional structure, its source and drain have a raised, three-dimensional structure called “fin.” Its gate is disposed so as to wrap around a channel region defined between the source and drain in this fin. In this fin structure, the channel region is defined by three surfaces of the fin, thereby improving channel controllability significantly compared to conventional ones. As a result, various advantages, including reducing the leakage power, increasing the ON-state current, and lowering the operating voltage, are achieved. This leads to improving the performance of the semiconductor integrated circuit.
U.S. Pat. No. 8,258,577 shows an exemplary standard cell including fin transistors (FIG. 2). Fins extending in the lateral direction are arranged in parallel with each other, and gate lines are arranged in the vertical direction.